1. Field of the Invention
The present invention relates to an information processing apparatus having a clock generating circuit and an information processing apparatus having a clock delaying circuit. More particularly, the present invention relates to an information processing apparatus having a clock generating circuit for controlling an oscillation frequency and the phase of an output clock by controlling a digital counter, and an information processing apparatus having a clock delaying circuit for controlling the phase of an output clock by controlling a digital counter.
2. Description of the Background Art
In association with an increase in the processing speed of an information processing apparatus of recent years, a PLL (Phase Locked Loop) circuit for generating a clock having the same frequency as a reference clock or a frequency which is a multiple of the frequency of the reference clock, synchronized with the reference clock is an indispensable circuit as a clock generating circuit in an information processing apparatus for performing a high-speed synchronizing process.
Conventionally, an analog PLL circuit for controlling oscillation frequency by controlling the voltage of a capacitor for holding a control voltage of a voltage controlled oscillation circuit (VCO) is widely used. However, it is difficult for the analog PLL circuit to perform control with a low voltage which is requested to the information processing apparatus of recent years. The analog PLL circuit has drawbacks such that it is sensitive to noise and it has very long waiting time until the operation is stabilized (a state in which the operation is stabilized is also referred to as a “locked state” and the waiting time until the lock state is obtained is also referred to as “lock time”).
As a technique for solving the drawbacks of the analog PLL circuit, a digital PLL circuit for controlling a delay amount of a delay circuit (hereinafter, also referred to as “delay line”) in which a plurality of inverters are connected in series by using a digital counter to control an oscillation frequency and the phase of an output clock has been proposed by the present inventors herein (Kouichi Ishimi and two others, “A Full-Digital PLL for Low Voltage LSIs”, Technical Report of IEICE, The Institute of Electronics, Information and Communication Engineers, ED97-45, SDM97-23, ICD97-35, pp. 29 to 36, June 1997).
In this digital PLL circuit, the count value of the digital counter before locking operation is zero (delay time of the delay line is the minimum) and is incremented by one every two cycles of a reference clock. The delay time of the delay line increases in proportional to the count value and, accordingly, the pulse width of an output clock increases. When the output clock becomes a predetermined multiple ratio of the reference clock, the PLL circuit is locked and increment of the count value is stopped.
Although the lock time has been improved as compared with that in the analog PLL circuit, there is still long waiting time. For example, when the digital counter is constructed by ten bits, 2048 cycles (=2×2010) are necessary at the maximum. In the case where the frequency is changed during operation of the PLL circuit or in the case where the PLL circuit is stopped in a low power mode, after that, the low power mode is canceled, and the PLL circuit is re-started, the locking operation has to be performed again. Each time the locking operation is performed, waiting time of the amount corresponding to the lock time occurs.
To deal with the problem, Japanese Patent Laying-Open No. 2000-244309 discloses a clock generating circuit capable of shortening lock time by providing a computing unit on the inside of a digital PLL circuit, calculating a count value in the locking operation by the computing unit, and setting the count value in a digital counter.
Japanese Patent Laying-Open No. 11-340823 discloses an information processing apparatus capable of monitoring a state value of a digital counter, that is, a phase adjustment value from an external diagnostic processor in order to diagnose whether an operation failure which occurs at the time of evaluating a system is caused by the PLL circuit or not.
As a circuit having a configuration similar to that of a digital PLL circuit, a DLL (Delay Locked Loop) circuit is generally known. In the case where an LSI is mounted on a system, the DLL circuit is a circuit for adjusting the phase of a system clock of the system on which the LSI is mounted and the phase of a clock supplied to an internal circuit of the LSI, and is provided on the inside of the LSI. For the DLL circuit as well, in a manner similar to the digital PLL circuit, a delay line in which a plurality of inverters are connected in series is provided. By controlling a delay amount of the delay line by using a digital counter, clock phase adjustment is performed.
In the case such that, if the lock time is long in the PLL circuit, the operating state of the PLL circuit is frequently changed such that the operation frequency is frequently changed or the circuit frequently shifts in a low power mode, deterioration in performance of the information processing apparatus is caused and power is consumed also in processes until a lock state is obtained, so that reduction in power consumption is checked.
The clock generating circuit (PLL circuit) disclosed in Japanese Patent Laying-Open No. 2000-244309 solves the problems. However, as a change in the operation state of the PLL circuit, there may be various changes according to the operation specification and operating environment of the information processing apparatus on which the PLL circuit is mounted such as a change in reference clock frequency, a change in a multiple ratio, a change in a power mode, a change in a power supply voltage, and a change in a temperature environment used. It is important that the user of the information processing apparatus can properly and flexibly makes settings of the PLL circuit in accordance with various changes in operating conditions.
The control range of the delay amount of the delay line is limited. When the necessary delay amount exceeds the control range, the PLL circuit operates erroneously. In a stationary state, the possibility that the delay amount exceeds the control range is low. However, in the case where a sudden temperature change, a sudden voltage change, or the like occurs, there is the possibility that the delay amount exceeds the control range. When such erroneous operation occurs, it is therefore important to detect the erroneous operation and take a proper countermeasure against the erroneous operation.
Such a situation similarly occurs in a digital DLL circuit having a delay line.